AD9515(Rev0) データシートの表示（PDF） - Analog Devices
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AD9515 Datasheet PDF : 28 Pages
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AD9515
Parameter
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 400 MHz
CMOS (OUT1) = 100 MHz
Divide = 4
Min Typ Max Unit
290
fs rms
Test Conditions/Comments
Delay off
Calculated from SNR of ADC method
CLK = 400 MHz
CMOS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0) = 50 MHz
DELAY BLOCK ADDITIVE TIME JITTER1
Delay FS = 1.5 ns Fine Adj. 00000
Delay FS = 1.5 ns Fine Adj. 11111
Delay FS = 5 ns Fine Adj. 00000
Delay FS = 5 ns Fine Adj. 11111
Delay FS = 10 ns Fine Adj. 00000
Delay FS = 10 ns Fine Adj. 11111
315
fs rms Calculated from SNR of ADC method
Interferer
100 MHz output; incremental additive jitter
0.71
ps rms
1.2
ps rms
1.3
ps rms
2.7
ps rms
2.0
ps rms
2.8
ps rms
1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
Min
Typ
SYNCB
Logic High
2.7
Logic Low
Capacitance
2
VREF
Output Voltage
0.62 VS
S0 TO S10
Levels
0
1/3
0.2 VS
2/3
0.55 VS
1
0.9 VS
Max
0.40
0.76 VS
0.1 VS
0.45 VS
0.8 VS
Unit Test Conditions/Comments
V
V
pF
V
Minimum − maximum from 0 mA to 1 mA load
V
V
V
V
Rev. 0 | Page 9 of 28
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