AD9525(Rev0) データシートの表示（PDF） - Analog Devices
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AD9525 Datasheet PDF : 48 Pages
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Data Sheet
AD9525
Table 47. SYNC_OUT Control
Reg.
Addr.
(Hex) Bits Bit Name
0x0F8 [7:5] Don’t care
4
SYNC_OUT
channel
power-down
3
Sync polarity
[2:1] SYNC_OUT
level
0
SYNC_OUT
driver
power-down
0x0F9 [7:5] Don’t care
4
Polarity CMOS
mode
[3:2] Enable CMOS
drivers
1
CMOS mode
0
Sync out
resampling
edge select
0x190 [7:0] Sync clock
S divider
0x191 [7:0] Sync clock
S divider
0x192 [7:5] Don’t care
4
Sync enable
[3:2] Sync source
[1:0] Sync mode
Description
Don’t care.
Powers down SYNC_OUT channel.
0: enabled.
1: power-down (default).
Polarity LVPECL mode.
0: noninverting (default).
1: inverting.
Bit 1 Bit 0 VOD (mV)
0
0
0
1
1
0
1
1
400 (default)
600
780
960
0: enabled (default).
1: powers down LVPECL SYNC_OUT driver.
Don’t care.
Polarity CMOS mode. This bit is also used in conjunction with Register 0x0F8[3] when the driver is in CMOS
mode (Register 0x0F9[1] = 1).
Reg. 0x0F9[4] Reg. 0x0F8[3] SYNC OUT/SYNC OUTB
0
0
Noninverting/noninverting
0
1
Inverting/inverting
1
0
Noninverting/inverting
1
1
Inverting/noninverting
Sets the CMOS driver output configuration when Register 0x0F9[1] = 1.
Bit 3 Bit 2 SYNC_OUT
SYNC_OUT
0
0
0
1
1
0
1
1
Tristate
On
Tristate
On
Tristate
Tristate
On
On
Use CMOS mode instead of LVPECL mode for SYNC_OUT.
0: LVPECL mode (default).
1: CMOS mode.
SYNC_OUT resample edge select. Selects the M divider output edge used to resample the sync clock.
0: use rising edge of M clock (default).
1: use falling edge of M clock.
16-bit sync S divider, Bits[7:0] (LSB).
Cycles of reference clock = S Divider Bits[15:0] + 1. For example, [15:0] = 0 is 1 reference clock cycles,
[15:0] = 1 is 2 reference clock cycles … [15:0] = 65535 is 65536 reference clock cycles.
16-bit sync S divider, Bits[15:8] (MSB).
Don’t care.
0: disable SYNC_OUT (default).
1: Enable SYNC_OUT.
Note: Self-clearing for single shot sync.
Bit 1 Bit 0 Select Reference for SYNC Clock
0
0
0
1
1
0
1
1
REF: reference input (default)
FB: PLL feedback N divider
Power-down: power down SYNC
Power-down: power down SYNC
Bit 1 Bit 0 Sync Mode
0
0
Single shot (default)
0
1
Periodic
1
0
Pseudorandom
1
1
Pseudorandom
Rev. 0 | Page 43 of 48
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