AD9627 データシートの表示（PDF） - Analog Devices
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AD9627 Datasheet PDF : 76 Pages
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AD9627
ADC DC SPECIFICATIONS—AD9627-125/AD9627-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
AD9627-125
Parameter
Temperature Min
Typ
Max Min
RESOLUTION
Full
12
12
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
±0.3
±0.6
Gain Error
Full
−0.7
−2.7
−3.9 −0.9
Differential Nonlinearity (DNL)1
Full
±0.4
25°C
±0.2
Integral Nonlinearity (INL)1
Full
±0.9
25°C
±0.4
MATCHING CHARACTERISTIC
Offset Error
25°C
±0.3
±0.6
Gain Error
25°C
±0.1
±0.75
TEMPERATURE DRIFT
Offset Error
Full
±15
Gain Error
Full
±95
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full
±5
±16
Load Regulation @ 1.0 mA
Full
7
INPUT REFERRED NOISE
VREF = 1.0 V
25°C
0.3
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
2
Input Capacitance2
Full
8
VREF INPUT RESISTANCE
Full
6
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
Full
1.7
1.8
1.9
1.7
DRVDD (CMOS Mode)
Full
1.7
3.3
3.6
1.7
DRVDD (LVDS Mode)
Full
1.7
1.8
1.9
1.7
Supply Current
IAVDD1, 3
Full
IDVDD1, 3
Full
IDRVDD1 (3.3 V CMOS)
Full
IDRVDD1 (1.8 V CMOS)
Full
IDRVDD1 (1.8 V LVDS)
Full
385
455
42
36
18
48
POWER CONSUMPTION
DC Input
Full
750
800
Sine Wave Input1 (DRVDD = 1.8 V) Full
814
Sine Wave Input1 (DRVDD = 3.3 V) Full
900
Standby Power4
Full
77
Power-Down Power
Full
2.5
6
AD9627-150
Typ
Max
Guaranteed
±0.2
±0.6
−3.2
−5.2
±0.9
±0.2
±1.3
±0.5
±0.2
±0.7
±0.2
±0.8
±15
±95
±5
±16
7
0.3
2
8
6
1.8
1.9
3.3
3.6
1.8
1.9
419
495
50
42
22
49
820
890
895
995
77
2.5
6
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3 The maximum limit applies to the combination of IAVDD and IDVDD currents.
4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. B | Page 6 of 76
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