AD9683 データシートの表示（PDF） - Analog Devices
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AD9683 Datasheet PDF : 44 Pages
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Data Sheet
CLOCK INPUT CONSIDERATIONS
The AD9683 has two options for deriving the input sampling clock:
a differential Nyquist sampling clock input or an RF clock input
(which is internally divided by 2 or 4). The clock input is selected in
Address 0x09 and by default is configured for the Nyquist clock
input. For optimum performance, clock the AD9683 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 48) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
Nyquist Clock Input Options
The AD9683 Nyquist clock input supports a differential clock
between 40 MHz to 625 MHz. The clock input structure supports
differential input voltages from 0.3 V to 3.6 V and is, therefore,
compatible with various logic family inputs, such as CMOS,
LVDS, and LVPECL. A sine wave input is also accepted, but
higher slew rates typically provide optimal performance. Clock
source jitter is a critical parameter that can affect performance, as
described in the Jitter Considerations section. If the inputs are
floated, pull the CLK− pin low to prevent spurious clocking.
The Nyquist clock input pins, CLK+ and CLK−, are internally
biased to 0.9 V and have a typical input impedance of 4 pF in
parallel with 10 kΩ (see Figure 48). The input clock is typically
ac-coupled to CLK+ and CLK−. Some typical clock drive circuits
are presented in Figure 49 through Figure 52 for reference.
AVDD
CLK+
4pF
0.9V
CLK–
4pF
Figure 48. Equivalent Nyquist Clock Input Circuit
For applications where a single-ended low jitter clock between
40 MHz to 200 MHz is available, an RF transformer is
recommended. An example using an RF transformer in the clock
network is shown in Figure 49. At frequencies above 200 MHz,
an RF balun is recommended, as seen in Figure 50. The back-to-
back Schottky diodes across the transformer secondary limit
clock excursions into the AD9683 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD9683,
yet preserves the fast rise and fall times of the clock, which are
critical to low jitter performance.
AD9683
CLOCK
INPUT
390pF
Mini-Circuits®
ADT1-1WT, 1:1Z
XFMR 390pF
50Ω 100Ω
390pF
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
CLK–
Figure 49. Transformer-Coupled Differential Clock (Up to 200 MHz)
390pF
CLOCK
INPUT
25Ω
390pF
ADC
CLK+
390pF
1nF
CLK–
25Ω
SCHOTTKY
DIODES:
HSMS2822
Figure 50. Balun-Coupled Differential Clock (Up to 625 MHz)
In some cases, it is desirable to buffer or generate multiple
clocks from a single source. In those cases, Analog Devices, Inc.,
offers clock drivers with excellent jitter performance. Figure 51
shows a typical PECL driver circuit that uses PECL drivers such
as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,
AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524,
and ADCLK905, ADCLK907, and ADCLK925.
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx
0.1µF PECL DRIVER
50kΩ
240Ω
0.1µF
ADC
CLK+
0.1µF
240Ω
100Ω
CLK–
Figure 51. Differential PECL Sample Clock (Up to 625 MHz)
Analog Devices also offers LVDS clock drivers with excellent jitter
performance. A typical circuit is shown in Figure 52. It uses
LVDS drivers such as the AD9510, AD9511, AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, and AD9524.
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx
0.1µF LVDS DRIVER
50kΩ
0.1µF
100Ω
0.1µF
ADC
CLK+
CLK–
Figure 52. Differential LVDS Sample Clock (Up to 625 MHz)
Rev. 0 | Page 21 of 44
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