AD9803 データシートの表示（PDF） - Analog Devices

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AD9803

CCD Signal Processor for Electronic Cameras

Analog Devices 

AD9803

SERIAL INTERFACE SPECIFICATIONS

SDATA

A0

A1

A2

D0

D1

D2

D3

D4

D5

D6

D7

SELECT

e0

e1

d0

d1

c0

c1

b0

b1

MODES

1

0

0

CLAMP

POWER DOWN

CLOCK

OUTPUT

LEVEL

MODES

MODES

MODES

f0

f1

f2

f3

f4

f5

f6

f7

PGA

0

1

0

PGA GAIN LEVEL SELECTION

g0

g1

g2

g3

g4

g5

g6

g7

DAC1

1

1

0

DAC1 INPUT

h0

h1

h2

h3

h4

h5

h6

h7

DAC2

0

0

1

DAC2 INPUT

m0

0

k0

j0

MODES21

1

1

1

OPERATION AND

POWER DOWN MODES

D8

D9

a0

a1

OPERATION

MODES

f8

f9

a0–a1

A-REG

b0–b1

B-REG

SELECT

c0–c1

C-REG

SHIFT REGISTER

NOTE

1MODES2 REGISTER BIT D1 MUST

BE SET TO ZERO.

d0–d1

e0–e1

f0–f9

D-REG

E-REG

F-REG

(a) OPERATION MODES

g0–g7

G-REG

(b) OUTPUT MODES

h0–h7

H-REG

(c) CLOCK MODES

j0

J-REG

(d) POWER DOWN MODES

k0

K-REG

(e) CLAMP LEVEL

(f) PGA GAIN

m0

M-REG

(g) DAC1 INPUT

(h) DAC2 INPUT

(j) EVEN-ODD OFFSET

CORRECTION

(k) EXTERNAL PGA

GAIN CONTROL

Figure 34. Internal Register Map

(m) DAC1 AND DAC2

POWER DOWN

SDATA

SCK

SL

RNW

A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

RISING EDGE

TRIGGERED

tDH

tDS

tLS

tLH

REGISTER LOADED ON

RISING EDGE

Figure 35. Serial WRITE Operation

DUMMY BITS

IGNORED

SDATA

RNW

A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 XX XX

SCK

SL

Figure 36. 16-Bit Serial WRITE Operation

–14–

REV. 0

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