AD9845AJST データシートの表示（PDF） - Analog Devices

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AD9845AJST

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

AD9845A

A/D Converter

The VGA gains up the signal level with respect to the 0.4 V bias

The AD9845A uses high-performance ADC architecture, opti- level. Signal levels above the bias level will be further increased

mized for high speed and low power. Differential Nonlinearity to a higher ADC code, while signal levels below the bias level

(DNL) performance is typically better than 0.5 LSB, as shown in will be further decreased to a lower ADC code.

TPC 2. Instead of the 1 V full-scale range used by the earlier

AD9801 and AD9803 products from Analog Devices, the

AD9845A’s ADC uses a 2 V input range. Better noise perfor-

mance results from using a larger ADC full-scale range (see

TPC 3).

AUX2 Mode

For sampling video-type waveforms, such as NTSC and PAL

signals, the AUX2 channel provides black level clamping, gain

adjustment, and A/D conversion. Figure 31 shows the circuit

configuration for using the AUX2 channel input (Pin 34). A

AUX1 Mode

external 0.1 µF blocking capacitor is used with the on-chip video

For applications that do not require CDS, the AD9845A can be clamp circuit, to level-shift the input signal to a desired refer-

configured to sample ac-coupled waveforms. Figure 30 shows ence level. The clamp circuit automatically senses the most

the circuit configuration for using the AUX1 channel input negative portion of the input signal, and adjusts the voltage

OBSOLETE (Pin 36). A single 0.1 µF ac-coupling capacitor is needed between

the input signal driver and the AUX1IN pin. An on-chip dc-bias

circuit sets the average value of the input signal to approximately

0.4 V, which is referenced to the midscale code of the ADC.

The VGA Gain register provides a gain range of 0 dB to 36 dB in

this mode of operation (see VGA Gain Curve, Figure 29).

across the input capacitor. This forces the black level of the

input signal to be equal to the value programmed into the Clamp

Level register (see Serial Interface Register Description). The VGA

provides gain adjustment from 0 dB to 18 dB. The same VGA

Gain register is used, but only the 9 MSBs of the gain register

are used (see Table VII.)

0.8V

INPUT SIGNAL

??V

0.1␮F AUX1IN

0.4V

5k⍀

0.4V

0.4V

0dB TO 36dB

VGA

10

VGA GAIN

ADC

MIDSCALE

REGISTER

Figure 30. AUX1 Circuit Configuration

MSB

D10

D9

X

0

1

1

REV. 0

VIDEO

SIGNAL

D8

X

0

1

VGA GAIN

REGISTER

AUX2IN

0.1␮F

BUFFER

9

0dB TO 18dB

VGA

ADC

VIDEO CLAMP

CIRCUIT

LPF

CLAMP LEVEL

8

REGISTER

CLAMP LEVEL

Figure 31. AUX2 Circuit Configuration

Table VII. VGA Gain Register Used for AUX2-Mode

D7

D6

D5

D4

D3

D2

D1

X

X

X

X

X

X

X

0

0

0

0

0

0

0

•

•

•

1

1

1

1

1

1

1

LSB

D0

X

0

1

Gain (dB)

0.0

0.0

•

•

•

18.0

–19–

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