AD9860 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
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AD9860 Datasheet PDF : 32 Pages
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AD9860/AD9862
PARAMETERS (continued)
Temp
POWER SUPPLY (continued)
Rx Path (fADC = 64 MSPS)
Processing Blocks Disabled
Decimation Filter Enabled
Hilbert Filter Enabled
Hilbert and Decimation Filter Enabled
25ºC
25ºC
25ºC
25ºC
NOTES
1% fDATA refers to the input data rate of the digital block.
2Interpolation filter stop band is defined by image suppression of 50 dB or greater.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Test
Level
III
III
III
III
AD9860/AD9862
Min
Typ
Max
9
15
16
18.5
(20 pF Load)
Minimum Reset Pulsewidth Low (tRL)
Digital Output Rise/Fall Time
DLL Output Clock
DLL Output Duty Cycle
Tx–/Rx–Interface (See Figures 11 and 12)
TxSYNC/TxIQ Setup Time (tTx1, tTx3)
TxSYNC/TxIQ Hold Time (tTx2, tTx4)
RxSYNC/RxIQ/IF to Valid Time(tRx1, tRx3)
RxSYNC/RxIQ/IF Hold Time (tRx2, tRx4)
Serial Control Bus (See Figures 1 and 2)
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulsewidth High (tHI)
Minimum Clock Pulsewidth Low (tLOW)
Maximum Clock Rise/Fall Time
Minimum Data/SEN Setup Time (tS)
Minimum SEN/Data Hold Time (tH)
Minimum Data/SCLK Setup Time (tDS)
Minimum Data Hold Time (tDH)
Output Data Valid/SCLK Time (tDV)
AUXILARY ADC
Conversion Rate
Input Range
Resolution
AUXILARY DAC
Settling Time
Output Range
Resolution
ADC TIMING
Latency (All Digital Processing Blocks Disabled)
DAC Timing
Latency (All Digital Processing Blocks Disabled)
Latency (2ϫ Interpolation Enabled)
Latency (4ϫ Interpolation Enabled)
Additional Latency (Hilbert Filter Enabled)
Additional Latency (Coarse Modulation Enabled)
Additional Latency (Fine Modulation Enabled)
Output Settling Time (TST) (to 0.1%)
Specifications subject to change without notice.
Temp
NA
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
Full
Full
Full
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
NA
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
AD9860/AD9862
Min
Typ
Max
5
2.8
4
32
128
50
3
3
5.2
0.2
16
30
30
1
25
0
25
0
30
1.25
3
10
8
3
8
7
3
30
72
36
5
8
35
Unit
mA
mA
mA
mA
Unit
Clock Cycles
ns
MHz
%
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
ns
ns
MHz
V
Bits
ms
V
Bits
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ns
–4–
REV. 0
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