AD9891KBC データシートの表示（PDF） - Analog Devices

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AD9891KBC

CCD Signal Processors with Precision Timing™ Generator

Analog Devices 

AD9891/AD9895

POSITION

PIXEL

PERIOD

RG

H1/H3

P[0]

RGr[0]

Hr[0]

P[12]

RGf[12]

CCD

SIGNAL

P[24]

P[36]

P[48] = P[0]

Hf[24]

SHP[28]

tS1

SHD[48]

NOTES

ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

Figure 10. High Speed Clock Default and Programmable Locations

H1/H3

H2/H4

tRISE

tPD < tRISE

FIXED CROSSOVER VOLTAGE

tPD

H1/H3

Figure 11. H-Clock Inverse Phase Relationship

H2/H4

P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

DCLK

tOD

DOUT

NOTES

DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

Figure 12. Digital Output Phase Adjustment

–14–

REV. A

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