AD9898KCP-20 データシートの表示（PDF） - Analog Devices

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AD9898KCP-20

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

AD9898

ADDRESS [7:0]

NUMBER WRITES N [23:0]

DATA 1 [31:0]

DATA 2 [31:0]

DATA N [31:0]

SDATA

SCK

SL

8-BIT

ADDRESS

NUMBER OF 32-BIT

DATA WRITES (N)

DATA 1 [31:0]

1

DATA 2 [31:0]

DATA N [31:0]

1

1

2

1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN.

2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.

Figure 8. System and Mode Register Writes

OPERATION OF VD SYNCHRONOUS TYPE

REGISTER WRITES BEGIN AT THE NEXT VD

FALLING EDGE.

VD

HD

CLI

PROGRAMMING OF VD SYNCHRONOUS

TYPE REGISTERS MUST BE COMPLETED

AT LEAST 4 CLI CYCLES BEFORE THE

FALLING EDGE OF VD.

Figure 9. VD Synchronous Type Register Writes

VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER

OPERATION

There are two types of control registers, VD synchronous and

VD asynchronous, as indicated in the address column of Table I.

Register writes to synchronous and asynchronous type registers

operate differently, as described below. Writes to system, Mode_A,

and Mode_B registers occur asynchronously.

Asynchronous Register Operation

For VD asynchronous register writes, SDATA data is stored

directly into the serial register at the rising edge of SL. As a

result, register operation begins immediately after the rising

edge of SL.

VD Synchronous Register Operation

For VD synchronous type registers, SDATA data is temporarily

stored in a buffer register at the rising edge of SL. This data is

held in the buffer register until the next falling edge of VD is

applied. Once the next falling edge of VD occurs, the buffered

SDATA data is loaded into the serial register and the register

operation begins (see Figure 9).

All control registers at the following addresses are VD Synchro-

nous type registers—Addr: 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E

(see Table I).

–18–

REV. 0

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