AD9898 データシートの表示（PDF） - Analog Devices

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AD9898

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

AD9898

VSUB CONTROL

The CCD readout bias (VSUB) can be programmed to accom-

modate different CCDs. VSUB ON and OFF toggle positions

and polarity are controlled using VSUBTOG (Addr 0x0D) and

VSUBPOL (Addr 0x0D) registers, respectively, as described in

Table XXIV. Since the VSUBTOG is an 11-bit register, the

VSUB ON position is programmable within any line. Figure 43

shows an example of controlling VSUB using these registers.

Table XXIV. VSUB Registers

Register Bit Register Range

Name

Width Type (Lines) Description

VSUBPOL 1

VSUBTOG 11

Control

(0 = Low, 1 = High)

Control 0–2048 VSUB Toggle Position

VSUB Placement and Polarity

Figure 43 shows the sequence of events for programming the

VSUB ON and OFF toggle positions and polarity.

1. Program VSUBTOG = 2 and VSUBPOL = 1.

2. Since VSUBTOG and VSUBPOL are VD synchronous type

registers, the falling edge of VD will update the serial writes

from Step 1 here.

3. VSUB will be asserted high after two HD cycles.

4. Program VSUBTOG = 3 and VSUBPOL = 0.

5. Since VSUBTOG and VSUBPOL are VD synchronous type

registers, the falling edge of VD will update the serial writes

from Step 4 here.

6. VSUB will be asserted low after three HD cycles.

1

SERIAL

WRITES

2

VD

HD

VSUB

3

2 LINES

4

Figure 43. VSUB Timing Example

5

6

3 LINES

REV. 0

–41–

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