AD9915-PCBZ データシートの表示（PDF） - Analog Devices
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AD9915-PCBZ Datasheet PDF : 47 Pages
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AD9915
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Performance .................................................................. 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Single Tone Mode ....................................................................... 17
Profile Modulation Mode .......................................................... 17
Digital Ramp Modulation Mode .............................................. 17
Parallel Data Port Modulation Mode....................................... 17
Programmable Modulus Mode................................................. 17
Mode Priority.............................................................................. 18
Functional Block Detail ................................................................. 19
DDS Core..................................................................................... 19
REVISION HISTORY
6/2016—Rev. E to Rev. F
Changes to Figure 17 and Figure 19............................................. 14
1/2016—Rev. D to Rev. E
Changes to DDS Core Section ...................................................... 19
Change to Figure 30 ....................................................................... 19
Updated Outline Dimensions ....................................................... 47
1/2014—Rev. C to Rev. D
Change to Maximum DAC Calibration Time Parameter ........... 5
Change to Figure 23 ....................................................................... 15
Changes to DAC Calibration Output Section............................. 20
Change to Address 0x02, Table 16................................................ 36
Changes to Table 19........................................................................ 43
11/2013—Rev. B to Rev. C
Changes to Table 2............................................................................ 5
Changes to Programming and Function Pins Section .............. 30
Data Sheet
12-Bit DAC Output .................................................................... 20
DAC Calibration Output........................................................... 20
Reconstruction Filter ................................................................. 20
Clock Input (REF_CLK/REF_CLK) ........................................ 21
PLL Lock Indication .................................................................. 22
Output Shift Keying (OSK)....................................................... 22
Digital Ramp Generator (DRG) ............................................... 23
Power-Down Control ................................................................ 27
Programming and Function Pins................................................. 28
Serial Programming ....................................................................... 31
Control Interface—Serial Input/Output ................................. 31
General Serial Input/Output Operation.................................. 31
Instruction Byte .......................................................................... 31
Serial Input/Output Port Pin Descriptions............................. 31
Serial Input/Output Timing Diagrams.................................... 32
MSB/LSB Transfers .................................................................... 32
Parallel Programming (8-/16-Bit) ................................................ 33
Multiple Chip Synchronization .................................................... 34
Register Map and Bit Descriptions .............................................. 36
Register Bit Descriptions ........................................................... 41
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
7/2013—Rev. A to Rev. B
Change to CMOS Logic Outputs Parameter, Table 1 ...................4
Changes to Table 2.............................................................................7
Changes to DDS Core Section ...................................................... 19
Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21
Changed PLL Charge Pump Section to PLL Charge Pump/
Total Feedback Divider Section; Changes to Table 8, PLL
Loop Filter Components Section, and Figure 34 ....................... 22
Change to Table 16 ......................................................................... 36
Changes to Bits [15:8], Table 19 ................................................... 43
8/2012—Rev. 0 to Rev. A
Changed External Clock Frequency from 3.5 GHz to 2.5 GHz
and Differential Input Voltage Unit from mV p-p to V p-p........4
Updated Outline Dimensions ....................................................... 47
7/2012—Revision 0: Initial Version
Rev. F | Page 2 of 47
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