AD9923ABBCZ(Rev0) データシートの表示（PDF） - Analog Devices

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AD9923ABBCZ
(Rev.:Rev0)

CCD Signal Processor with V-Driver and Precision Timing™ Generator

Analog Devices 

AD9923A

CCD

SIGNAL

RG

HL/H1/H3

H2/H4

NOTES

1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 19. 2-Phase H-Clock Operation

POSITION

PIXEL

PERIOD

RG

HL/H1/H3

P[0]

RGr[0]

Hr[0]

P[12]

RGf[12]

P[24]

Hf[24]

P[36]

P[48] = P[0]

H2/H4

CCD

SIGNAL

SHP[24]

tS1

SHD[48]

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

Figure 20. High Speed Timing Default Locations

Rev. 0 | Page 16 of 88

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