AD9923A(Rev0) データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD9923A
(Rev.:Rev0)

CCD Signal Processor with V-Driver and Precision Timing™ Generator

Analog Devices 

P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

DCLK

tOD

DOUT

NOTES

1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

3. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

Figure 21. Digital Output Phase Adjustment

AD9923A

CLI

tCLIDLY

N

CCDIN

N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17

SHD

(INTERNAL)

SAMPLE PIXEL N

ADC DOUT

(INTERNAL)

DCLK

D[0:11]

N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

tDOUTINH

PIPELINE LATENCY = 16 CYCLES

N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT WITH RESPECT TO CLI LOCATION.

3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY tDOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT

THE 12 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

5. RECOMMENDED VALUE FOR tOD (DOUT DLY) IS 4ns.

6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT

THE DATA OUTPUT PINS. THIS CONFIGURATION IS RECOMMENDED IF THE ADJUSTABLE DOUT PHASE IS NOT REQUIRED.

Figure 22. Digital Data Output Pipeline Delay

Rev. 0 | Page 17 of 88

Share Link: