AD9923ABBCZ データシートの表示（PDF） - Analog Devices

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AD9923ABBCZ

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

CLI

tCLIDLY

N

CCDIN

N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17

SHD

(INTERNAL)

SAMPLE PIXEL N

ADC DOUT

(INTERNAL)

DCLK

D[0:11]

N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

tDOUTINH

PIPELINE LATENCY = 16 CYCLES

N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT WITH RESPECT TO CLI LOCATION.

3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY tDOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT

THE 12 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

5. RECOMMENDED VALUE FOR tOD (DOUT DLY) IS 4ns.

6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT

THE DATA OUTPUT PINS. THIS CONFIGURATION IS RECOMMENDED IF THE ADJUSTABLE DOUT PHASE IS NOT REQUIRED.

Figure 22. Digital Data Output Pipeline Delay

HORIZONTAL CLAMPING AND BLANKING

The AD9923A horizontal clamping and blanking pulses are

fully programmable to suit a variety of applications. Individual

controls are provided for CLPOB, PBLK, and HBLK during

different regions of each field. This allows dark pixel clamping

and blanking patterns to be changed at each stage of the readout

to accommodate different image transfer timing and high speed

line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 23. These two signals are independently

programmed using the registers in Table 12. SPOL is the start

polarity for the signal, and TOG1 and TOG2 are the first and

second toggle positions of the pulse. Both signals are active low

and should be programmed accordingly.

A separate pattern for CLPOB and PBLK can be programmed

for each V-sequence. As described in the Vertical Timing

Generation section, several V-sequences can be created, each

containing a unique pulse pattern for CLPOB and PBLK.

Figure 46 shows how the sequence change positions divide the

readout field into regions. A different V-sequence can be

assigned to each region, allowing the CLPOB and PBLK signals

to change with each change in the vertical timing. Unused CLPOB

and PBLK toggle positions should be set to 8191.

CLPOB and PBLK Masking Area

The AD9923A allows the CLPOB and/or PBLK signals to be

disabled during certain lines in the field without changing the

existing CLPOB and/or PBLK pattern settings.

To use CLPOB masking, the CLPMASKSTART and CLPMASKEND

registers are programmed to specify the starting and ending lines

in the field where the CLPOB patterns are ignored. There are three

sets of CLPMASKSTART and CLPMASKEND registers,

allowing up to three CLPOB masking areas to be created.

CLPOB masking registers are not specific to a given V-sequence;

they are active for any existing field of timing. To disable the

CLPOB masking feature, set these registers to the maximum

value, 0xFFF (default value).

To use PBLK masking, the PBLKMASKSTART and

PBLKMASKEND registers are programmed to specify the

starting and ending lines in the field where the PBLK patterns

are ignored. There are three sets of PBLKMASKSTART and

PBLKMASKEND registers, allowing the creation of up to three

PBLK masking areas.

PBLK masking registers are not specific to a given V-sequence;

they are active for any existing field of timing. To disable the

PBLK masking feature, set these registers to the maximum

value, 0xFFF (default value).

Rev. A | Page 18 of 84

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