CCD MODE TIMING
AD9943/AD9944
CCD
SIGNAL
tID
N
tID
SHP
tS1
SHD
N+1
tS2
N+2
tCP
N+9
N + 10
DATACLK
tOD
OUTPUT
DATA
N – 10
N–9
N–8
N– 1
N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 14. CCD Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 15. Typical CCD Mode Line Clamp Timing
EFFECTIVE DATA
Rev. B | Page 17 of 20