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AD9948KCPZ データシートの表示(PDF) - Analog Devices

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AD9948KCPZ Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN CONFIGURATION
NC 1
(LSB) D0 2
D1 3
D2 4
DRVSS 5
DRVDD 6
D3 7
D4 8
D5 9
D6 10
PIN 1
IDENTIFIER
AD9948
TOP VIEW
30 REFB
29 REFT
28 AVSS
27 CCDIN
26 AVDD
25 CLI
24 TCVDD
23 TCVSS
22 RGVDD
21 RG
AD9948
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type*
Description
2–4
5
6
7–13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1, 40
D0–D2
DO
DRVSS
P
DRVDD
P
D3–D9
DO
H1
DO
H2
DO
HVSS
P
HVDD
P
H3
DO
H4
DO
RGVSS
P
RG
DO
RGVDD
P
TCVSS
P
TCVDD
P
CLI
DI
AVDD
P
CCDIN
AI
AVSS
P
REFT
AO
REFB
AO
SL
DI
SDI
DI
SCK
DI
VD
DI
HD
DI
DVSS
P
DVDD
P
HBLK
DI
CLP/PBLK
DO
NC
Data Outputs (D0 is LSB)
Digital Driver Ground
Digital Driver Supply
Data Outputs (D9 is MSB)
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1–H4 Driver Ground
H1–H4 Driver Supply
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Reset Gate Clock
RG Driver Supply
Analog Ground for Timing Core
Analog Supply for Timing Core
Master Clock Input
Analog Supply for AFE
Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
Analog Ground for AFE
Reference Top Decoupling (Decouple with 1.0 µF to AVSS)
Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
3-Wire Serial Load
3-Wire Serial Data Input
3-Wire Serial Clock
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground
Digital Supply
Optional HBLK Input
CLPOB or PBLK Output
Not Internally Connected
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–5–

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