AD9953(RevB) データシートの表示（PDF） - Analog Devices
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AD9953 Datasheet PDF : 32 Pages
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AD9953
Data Sheet
CFR2<1:0>: Charge Pump Current Control Bits
These bits are used to control the current setting on the charge
pump. The default setting, CFR2<1:0>, sets the charge pump
current to the default value of 75 µA. For each bit added (01, 10,
11), 25 µA of current is added to the charge pump current:
100 µA, 125 µA, and 150 µA.
Other Register Descriptions
Amplitude Scale Factor (ASF)
The ASF register stores the 2-bit auto ramp rate speed value
and the 14-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto OSK operation, ASF <15:14>
tells the OSK block how many amplitude steps to take for each
increment or decrement. For ASF<15:14> = {00, 01, 10, 11}, the
increment/decrement is set to {1, 2, 4, 8}, respectively. ASF
<13:0> sets the maximum value achievable by the OSK internal
multiplier. In manual OSK mode, ASF<15:14> has no effect.
ASF <13:0> provides the output scale factor directly. If the OSK
enable bit is cleared, CFR1<25> = 0, this register has no effect
on device operation.
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal. The
exact value of phase offset is given by the following formula:
Φ
=
POW
214
×
360°
RAM Segment Control Words (RSCW0, RSCW1, RSCW2,
and RSCW3)
When the linear sweep enable bit CFR1<21> is clear,
Registers 0x07, 0x08, 0x09, and 0x0A act as the RAM segment
control words for each of the RAM segments. Each of the RAM
segment control words is comprised of a RAM segment address
ramp rate, a final address value, a beginning address value, a
RAM segment mode control, and a no-dwell bit.
RAM Segment Address Ramp Rate, RSCW<39:24>
For RAM modes that step through address values, such as
ramping, this 16-bit word defines the number of SYNC_CLK
cycles the RAM controller dwells at each address. A value of 0 is
invalid. Any other value from 1 to 65535 may be used.
RAM Segment Final Address RSCW<9:8>, RSCW<23:16>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are listed is the order in which the bits must be written.
RSCW<23>, even though during the write operation is more
significant than RSCW<9>, is only the third MSB of the final
address value. RSCW<9>, even though it comes later in the
RSCW than RSCW<23>, is the MSB of the final address value.
RAM Segment Beginning Address RSCW<3:0>, <15:10>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are listed is the order in which the bits must be written.
RSCW<15>, even though during the write operation is more
significant than RSCW<3>, is only the fifth MSB of the final
address value. RSCW<3>, even though it comes later in the
RSCW than RSCW<15>, is the MSB of the final address value.
RAM Segment Mode Control RSCW<7:5>
This 3-bit sequence determines the RAM segment’s mode of
operation. There are only five possible RAM modes, so only
values of 0 to 5 are valid. See Table 6 to determine the bit
combination for various RAM modes.
RAM Segment No-Dwell Bit RSCW<4>
This bit sets the no-dwell feature of sweeping profiles. In
profiles that sweep from a defined beginning to a defined end,
the RAM controller can either dwell at the final address until
the next profile is selected or, when this bit is set, the RAM
controller will return to the beginning address and dwell there
until the next profile is selected.
RAM
The AD9953 incorporates a 1024 × 32 block of SRAM. The
RAM is a bidirectional single port. Both read and write
operations from and to the RAM are valid, but they cannot
occur simultaneously. Write operations from the serial I/O port
have precedence, and if an attempt to write to RAM is made
during a read operation, the read operation will be halted. The
RAM is controlled in multiple ways, dictated by the modes of
operation described in the RAM Segment Control Word <7:5>
as well as data in the control function register. Read/write
control for the RAM will be described for each mode
supported.
When the RAM enable bit (CFR1<31>) is set, the RAM output
optionally drives the input to the phase accumulator or the
phase offset adder, depending on the state of the RAM destina-
tion bit (CFR1<30>). If CFR1<30> is a Logic 1, the RAM output
is connected to the phase offset adder and supplies the phase
offset control word(s) for the device. When CFR1<30> is
Logic 0 (default condition), the RAM output is connected to the
Rev. B | Page 18 of 32
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