AD9958BCPZ データシートの表示（PDF） - Analog Devices

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AD9958BCPZ

500 MSPS Direct Digital Synthesizer

Analog Devices 

AD9958

SPECIFICATIONS

AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS

(REFCLK multiplier bypassed), unless otherwise noted.

Table 1.

Parameter

REFERENCE CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Bypassed

REFCLK Multiplier Enabled

Internal VCO Output Frequency Range

VCO Gain Control Bit Set High1

VCO Gain Control Bit Set Low1

Crystal REFCLK Source Range

Input Level

Input Voltage Bias Level

Input Capacitance

Input Impedance

Duty Cycle with REFCLK Multiplier Bypassed

Duty Cycle with REFCLK Multiplier Enabled

CLK Mode Select (Pin 24) Logic 1 Voltage

CLK Mode Select (Pin 24) Logic 0 Voltage

DAC OUTPUT CHARACTERISTICS

Resolution

Full-Scale Output Current

Gain Error

Channel-to-Channel Output Amplitude Matching Error

Output Current Offset

Differential Nonlinearity

Integral Nonlinearity

Output Capacitance

Voltage Compliance Range

Channel-to-Channel Isolation

WIDEBAND SFDR

Min

Typ

1

10

255

100

20

200

1.15

2

1500

45

35

1.25

1.25

−10

−2.5

1

±0.5

±1.0

3

AVDD −

0.50

72

1 MHz to 20 MHz Analog Output

−65

20 MHz to 60 MHz Analog Output

−62

60 MHz to 100 MHz Analog Output

−59

100 MHz to 150 MHz Analog Output

−56

150 MHz to 200 MHz Analog Output

−53

NARROW-BAND SFDR

1.1 MHz Analog Output (±10 kHz)

−90

1.1 MHz Analog Output (±50 kHz)

−88

1.1 MHz Analog Output (±250 kHz)

−86

1.1 MHz Analog Output (±1 MHz)

−85

15.1 MHz Analog Output (±10 kHz)

−90

15.1 MHz Analog Output (±50 kHz)

−87

15.1 MHz Analog Output (±250 kHz)

−85

15.1 MHz Analog Output (±1 MHz)

−83

40.1 MHz Analog Output (±10 kHz)

−90

40.1 MHz Analog Output (±50 kHz)

−87

40.1 MHz Analog Output (±250 kHz)

−84

40.1 MHz Analog Output (±1 MHz)

−82

75.1 MHz Analog Output (±10 kHz)

−87

Max

Unit

500

MHz

125

MHz

500

MHz

160

MHz

30

MHz

1000

mV

V

pF

Ω

55

%

65

%

1.8

V

0.5

V

10

Bits

10

mA

+10

% FS

+2.5

%

25

μA

LSB

LSB

pF

AVDD + V

0.50

dB

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

dBc

Test Conditions/Comments

See Figure 34 and Figure 35

Measured at each pin (single-ended)

1.8 V digital input logic

1.8 V digital input logic

Must be referenced to AVDD

DAC supplies tied together (see Figure 19)

The frequency range for wideband SFDR

is defined as dc to Nyquist

Rev. A | Page 4 of 44

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