AD9958BCPZ データシートの表示（PDF） - Analog Devices
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AD9958BCPZ Datasheet PDF : 44 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC_IN 1
SYNC_OUT 2
MASTER_RESET 3
PWR_DWN_CTL 4
AVDD 5
AGND 6
AVDD 7
CH0_IOUT 8
CH0_IOUT 9
AGND 10
AVDD 11
AGND 12
CH1_IOUT 13
CH1_IOUT 14
PIN 1
INDICATOR
AD9958
TOP VIEW
(Not to Scale)
42 P2
41 P1
40 P0
39 AVDD
38 NC
37 AVDD
36 AVDD
35 AVDD
34 NC
33 AVDD
32 NC
31 AVDD
30 AVDD
29 AVDD
AD9958
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN
ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
3. NC = NO CONNECT.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC_IN
2
SYNC_OUT
3
MASTER_RESET
4
5, 7, 11, 15, 19, 21,
26, 29, 30, 31, 33,
35, 36, 37, 39
6, 10, 12, 16, 18,
20, 25
45, 55
44, 56
8
9
13
14
17
22
PWR_DWN_CTL
AVDD
AGND
DVDD
DGND
CH0_IOUT
CH0_IOUT
CH1_IOUT
CH1_IOUT
DAC_RSET
REF_CLK
23
REF_CLK
I/O1 Description
I
Used to Synchronize Multiple AD9958 Devices. Connects to the SYNC_OUT pin of
the master AD9958 device.
O
Used to Synchronize Multiple AD9958 Devices. Connects to the SYNC_IN pin of the
slave AD9958 devices.
I
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9958 internal
registers to their default state, as described in the Register Maps and Bit Descriptions
section.
I
External Power-Down Control.
I
Analog Power Supply Pins (1.8 V).
I
Analog Ground Pins.
I
Digital Power Supply Pins (1.8 V).
I
Digital Power Ground Pins.
O
True DAC Output. Terminates into AVDD.
O
Complementary DAC Output. Terminates into AVDD.
O
True DAC Output. Terminates into AVDD.
O
Complementary DAC Output. Terminates into AVDD.
I
Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated
in single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
I
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended
mode, this is the input. See the Modes of Operation section for the reference clock
configuration.
Rev. A | Page 9 of 44
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