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ADF41020BCPZ-RL7(Rev0) データシートの表示(PDF) - Analog Devices

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ADF41020BCPZ-RL7
(Rev.:Rev0)
ADI
Analog Devices ADI
ADF41020BCPZ-RL7 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF41020
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
GND 1
GND 2
GND 3
RFIN 4
GND 5
ADF41020
TOP
VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 3, 5, 9, 10 GND
Ground Pins.
4
RFIN
Input to the RF Prescaler. This input is ac-coupled internally.
6, 7
AVDD
Analog Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. Pin 6 is the supply for the fixed divide-by-4 prescaler.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ (see Figure 9). This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, PD1.
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches with the latch being selected using the control bits.
15
MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
16, 17
18
19
DVDD
VP
RSET
Digital Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply.
Connecting a resistor between this pin and GND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
ICP MAX
=
25.5
RSET
So, with RSET = 5.1 kΩ, ICP MAX = 5.0 mA.
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the
external VCO.
EP
Exposed Pad. The exposed pad must be connected to GND.
Rev. 0 | Page 6 of 16

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