E28F001BN データシートの表示（PDF） - Intel
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E28F001BN Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
AC CHARACTERISTICS Write Erase Program Operations(1 9)
Versions
Symbol
VCC g10%(10)
28F001BX-120 28F001BX-150
Unit
Parameter
Notes Min Max Min Max
tAVAV tWC Write Cycle Time
120
150
ns
tPHWL tPS RP High Recovery to WE Going Low
2
480
480
ns
tELWL tCS CE Setup to WE Going Low
10
10
ns
tWLWH tWP WE Pulse Width
50
50
ns
tPHHWH tPHS RP VHH Setup to WE Going High
2
100
100
ns
tVPWH tVPS VPP Setup to WE Going High
2
100
100
ns
tAVWH tAS Address Setup to WE Going High
3
50
50
ns
tDVWH tDS Data Setup to WE Going High
4
50
50
ns
tWHDX tDH Data Hold from WE High
10
10
ns
tWHAX tAH Address Hold from WE High
10
10
ns
tWHEH tCH CE Hold from WE High
10
10
ns
tWHWL tWPH WE Pulse Width High
50
50
ns
tWHQV1
Duration of Programming Operation
5 6 7 15
15
ms
tWHQV2
Duration of Erase Operation (Boot)
5 6 7 13
13
sec
tWHQV3
Duration of Erase Operation (Parameter) 5 6 7 1 3
13
sec
tWHQV4
Duration of Erase Operation (Main)
5 6 7 30
30
sec
tWHGL
Write Recovery before Read
0
0
ms
tQVVL tVPH VPP Hold from Valid SRD
26
0
0
ns
tQVPH tPHH RP VHH Hold from Valid SRD
27
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100 ns
PROM Programmer Specifications
Versions
Symbol
Parameter
VCC g10%
28F001BX-120 28F001BX-150
Unit
Notes Min Max Min Max
tGHHWL
tWHGH
OE VHH Setup to WE Going Low
OE VHH Hold from WE High
2 8 480
2 8 480
480
ns
480
ns
NOTES
1 Read timing characteristics during erase and program operations are the same as during read-only operations Refer to
AC Characteristics for Read-Only Operations
2 Sampled not 100% tested
3 Refer to Table 3 for valid AIN for byte programming or block erasure
4 Refer to Table 3 for valid DIN for byte programming or block erasure
5 The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory including byte program and verify (programming) and block precondition precondition verify erase and erase
verify (erasing)
6 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of
program erase success (SR 3 4 5 e 0)
7 For boot block programming and erasure RP should be held at VHH until determination of program erase success
(SR 3 4 5 e 0)
8 Alternate boot block access method
9 Erase Program Cycles on extended temperature products is 10 000 cycles
10 See standard test configuration
24
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