ADN2805(Rev0) データシートの表示（PDF） - Analog Devices
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ADN2805 Datasheet PDF : 16 Pages
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Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP and REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN output traces to be
matched in length to avoid skew between the differential traces.
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 15).
A 0.1 μF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
ADN2805
VCC
TIA
ADN2805
50Ω CIN PIN
50Ω CIN NIN
50Ω 50Ω
0.1µF
VREF
3kΩ
2.5V
Figure 15. AC-Coupled Input Configuration
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
VCC
TIA
V1 CIN V2 PIN
ADN2805
+
V1b CIN V2b
50Ω
VREF BUFFER
50Ω
CDR
–
NIN
COUT
COUT
DATAOUTP
DATAOUTN
1
2
V1
V1b
V2
V2b
VDIFF
3
4
VREF
VTH
VDIFF = V2 – V2b
VTH = ADN2805 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2805. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 16. Example of Baseline Wander
Rev. 0 | Page 15 of 16
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