ADN2812(Rev0) データシートの表示（PDF） - Analog Devices

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ADN2812
(Rev.:Rev0)

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2812

Use the following equation to determine the data rate:

( ) f DATARATE = FREQ [22..0]× f REFCLK / 2(14+SEL _ RATE)

where:

FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),

FREQ1[7:0], and FREQ0[7:0] (LSByte).

Table 12.

D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0

FREQ2[6:0]

FREQ1[7:0]

FREQ0[7:0]

fDATARATE is the data rate (Mb/s).

fREFCLK is the REFCLK frequency (MHz).

SEL_RATE is the setting from CTRLA[7:6].

For example, if the reference clock frequency is 32 MHz,

SEL_RATE = 1, since the CTRLA[7:6] setting would be [01],

because the reference frequency would fall into the 25 MHz to

50 MHz range. Assume for this example that the input data rate

is 2.488 Gb/s (OC-48). After following Steps 1 through 4, the

value that is read back on FREQ[22:0] = 0x26E010, which is

equal to 2.5477 × 106. Plugging this value into the equation

yields

( ) ( ) 2.5477e6 × 32e6 / 2(14+1) = 2.488 Gb/s

If subsequent frequency measurements are required, CTRLA[1]

should remain set to 1. It does not need to be reset. The

measurement process is reset by writing a 1 followed by a 0 to

CTRLB[3]. This initiates a new data rate measurement. Follow

Steps 2 through 4 to read back the new data rate.

Note: A data rate readback is valid only if LOL is low. If LOL is

high, the data rate readback is invalid.

Additional Features Available via the I2C Interface

Coarse Data Rate Readback

The data rate can be read back over the I2C interface to

approximately +10% without the need of an external reference

clock. A 9-bit register, COARSE_RD[8:0], can be read back

when LOL is de-asserted. The 8 MSBs of this register are the

contents of the RATE[7:0] register. The LSB of the

COARSE_RD register is Bit MISC[0].

Table 13 provides coarse data rate readback to within ±10%.

LOS Configuration

The LOS detector output, LOS Pin 22, can be configured to be

either active high or active low. If CTRLC[2] is set to Logic 0

(default), the LOS pin is active high when a loss of signal

condition is detected. Writing a 1 to CTRLC[2] configures the

LOS pin to be active low when a loss of signal condition is

detected.

System Reset

A frequency acquisition can be initiated by writing a 1 followed

by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new

frequency acquisition while keeping the ADN2812 in the

operating mode that it was previously programmed to in

registers CTRL[A], CTRL[B], and CTRL[C].

Rev. 0 | Page 20 of 28

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