EVAL-ADN2817EBZ データシートの表示（PDF） - Analog Devices

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EVAL-ADN2817EBZ

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

Analog Devices 

Data Sheet

ADN2817/ADN2818

Table 15. Mode Select Register, SEL_MODE

D7

Set to 0

D6

Set to 0

D5

Set to 0

D4

Set to 0

D3

Default 0

Limited rate enable = 1

D2

Set to 0

CLK Holdover Mode

D1

Set to 1 for clock holdover mode

D0

Set to 0

Table 16. BER Control Register, BERCTLA

BER Timer (NUMBITS)

D7 D6 D5 No. of Bits

0 0 0 218 bits

0 0 1 221 bits

0 1 0 224 bits

0 1 1 227 bits

1 0 0 230 bits

1 0 1 233 bits

1 1 0 236 bits

1 1 1 239 bits

D4

Set to 0

BER Start Pulse

D3

Write a 1 followed by a 0 to initiate BER measurement

Error Count Byte Select

(NUMERRORS[39:0])

D2 D1 D0 Byte Selection

0 0 0 Byte 0

0 0 1 Byte 1

0 1 0 Byte 2

0 1 1 Byte 3

1 0 0 Byte 4

Rev. E | Page 17 of 40

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