ADN2819(RevC) データシートの表示（PDF） - Analog Devices

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ADN2819
(Rev.:RevC)

Multirate to 2.7 Gbps Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

Data Sheet

DC-COUPLED APPLICATION

The inputs to the ADN2819 can also be dc-coupled. This may

be necessary in burst mode applications where there are long

periods of CIDs and baseline wander cannot be tolerated. If the

inputs to the ADN2819 are dc-coupled, care must be taken not

to violate the input range and common-mode level requirements

of the ADN2819 (see Figure 26, Figure 27, and Figure 28). If dc-

coupling is required, and the output levels of the TIA do not adhere

to the levels shown in Figure 27 and Figure 28, there needs to be

level shifting and/or an attenuator between the TIA outputs and

the ADN2819 inputs.

LOL TOGGLING DURING LOSS OF INPUT DATA

If the input data stream is lost due to a break in the optical link

(or for any reason), the clock output from the ADN2819 will

stay within 1000 ppm of the VCO center frequency as long as

there is a valid reference clock. The LOL pin toggles at a rate of

several kHz because the LOL pin toggles between a Logic 1 and

a Logic 0, while the frequency loop and phase loop swap control

of the VCO. The chain of events is as follows:

• The ADN2819 is locked to the input data stream; LOL = 0.

• The input data stream is lost due to a break in the link. The

VCO frequency drifts until the frequency error is greater

than 1000 ppm. LOL is asserted to a Logic 1 as control of

the VCO is passed back to the frequency loop.

• The frequency loop pulls the VCO to within 500 ppm of

the center frequency. Control of the VCO is passed back to

the phase loop and LOL is deasserted to a Logic 0.

• The phase loop tries to acquire, but there is no input data

present so the VCO frequency drifts.

• The VCO frequency drifts until the frequency error is

greater than 1000 ppm. LOL is asserted to a Logic 1 as

control of the VCO is passed back to the frequency loop.

This process is repeated until a valid input data stream is

re-established.

ADN2819

VCC

TIA

50Ω

50Ω

0.1µ F

ADN2819

PIN

NIN

50Ω 50Ω

VREF

INPUT (V)

Figure 26. ADN2819 with DC-Coupled Inputs

V p-p = PIN – NIN = 2 × VSE = 10mV AT SENSITIVITY

PIN

VSE = 5mV MIN

VCM = 0.4V MIN

(DC-COUPLED)

NIN

Figure 27. Minimum Allowed DC-Coupled Input Levels

INPUT (V)

PIN

V p-p = PIN – NIN = 2 × VSE = 2.4V MAX

VSE = 1.2V MAX

VCM = 0.6V

(DC-COUPLED)

NIN

Figure 28. Maximum Allowed DC-Coupled Input Levels

Rev. C | Page 21 of 25

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