ADP3026 データシートの表示（PDF） - Analog Devices

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ADP3026

High Efficiency Dual Power Supply Controller

Analog Devices 

ADP3026

Table 8. Recommended Capacitor Manufacturers

Maximum Output Current

2A

Input Capacitor

TOKIN Multilayer

Ceramic Cap, 22 µF/25 V

P/N:C55Y5U1E226Z

TAIYO YUDEN INC.

Ceramic Caps, Y5V Series 10 µF/25 V

P/N: TMK432BJ106KM

Output Capacitor

SANYO POSCAP TPC

3.3 V Output

Series, 68 µF/10 V

Output Capacitor

SANYO POSCAP TPC

5 V Output

Series, 68 µF/10 V

4A

TOKIN Multilayer

Ceramic Cap, 2 × 22 µF/25 V

P/N:C55Y5U1E226Z

TAIYO YUDEN INC.

Ceramic Caps, Y5V Series 10 µF/25 V

P/N: TMK432BJ106KM

SANYO POSCAP TPC

Series, 2 × 68 µF/10 V

SANYO POSCAP TPC

Series,2 × 68 µF/10 V

Power MOSFET Selection

N-channel power MOSFETs are used for both the main and

synchronous switches. The important selection parameters for

the power MOSFETs are threshold voltage (VGS(TH)) and on

resistance (RDS(ON)). An internal LDO regulator generates a 5 V

supply that is boosted above the input voltage using a bootstrap

circuit. This floating 5 V supply is used for the upper (main)

MOSFET gate drive. Logic-level threshold MOSFETs must be

used for both the main and synchronous switches.

Maximum output current (IMAX) determines the RDS(ON)

requirement for the two power MOSFETs. When the ADP3026

is operating in continuous mode, the simplifying assumption

can be made that one of the two MOSFETs is always conducting

the load current. The duty cycles for the MOSFETs are given by

Upper MOSFET Duty Cycle = V OUT

(10)

V IN

Lower MOSFET Duty Cycle = V IN −V OUT

(11)

V IN

From the duty cycle, the required minimum RDS(ON) for each

MOSFET can be derived by the following equations:

Upper MOSFET:

RDS(ON )(Upper)

=

V OUT

×

V IN × PD

I MAX2 × (1×

α∆T )

(12)

Lower MOSFET:

RDS(ON )(Lower)

=

(V

IN

V IN × PD

− V OUT) × I MAX2

× (1 +

α∆T )

(13)

where PD is the allowable power dissipation and α is the

temperature dependency of RDS(ON). PD is determined by

efficiency and/or thermal requirements (see the Efficiency

Enhancement section). (1 + α∆T) is generally given for a

MOSFET in the form of a normalized RDS(ON) versus

temperature curve, but α = 0.007/°C can be used as an

approximation for low voltage MOSFETs.

Maximum MOSFET power dissipation occurs at maximum

output current, and is calculated as follows:

Upper MOSFET:

PD

(Upper)

=

V OUT

V IN

×

I MAX2

×

RDS(ON )

× (1

+

α∆T )

(14)

Lower MOSFET:

P D (Lower) = V IN − V OUT × I MAX 2 × RDS(ON) × (1 + α∆T ) (15)

V IN

The Schottky diode, D1 in Figure 15, conducts only during the

dead time between conduction of the two power MOSFETs.

D1’s purpose is to prevent the body diode of the lower N-

channel MOSFET from turning on and storing charge during

the dead time, which could cost as much as 1% in efficiency. D1

should be selected for a forward voltage of less than 0.5 V when

conducting IMAX. Recommended transistors for upper and lower

MOSFETs are given in Table 9.

Table 9. Recommended MOSFETs

Maximum Output 2 A

4A

Vishay/Siliconix

Si4412DY,

28 mΩ

Si4410DY,

13.5 mΩ

International

Rectifier

IRF7805,

11 mΩ

IRF7811,

8.9 mΩ

IRF7805,

11 mΩ

10 A

Si4874DY,

7.5 mΩ

IRFBA3803,

5.5 mΩ

IRF7809,

7.5 mΩ

Soft Start

The soft start time of each switching regulator is programmed

by connecting a soft start capacitor to the corresponding soft

start pin (SS3 or SS5). The time it takes each regulator to ramp

up to its full duty ratio depends proportionally on the values of

the soft start capacitors. The charging current is 2.5 µA ±20%.

The capacitor value to set a given soft start time, tSS, is given by

CSS

=

2.5

µA

(t SS(ms))

1.8 V

(pF)

(16)

Rev. 0 | Page 14 of 20

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