ADSP-21261SKBC-150 データシートの表示（PDF） - Analog Devices

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ADSP-21261SKBC-150

SHARC® Embedded Processor

Analog Devices 

ADSP-21261

PIN FUNCTION DESCRIPTIONS

ADSP-21261 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-

tified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST). Tie or pull unused inputs to

VDDEXT or GND, except for the following:

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI,

and AD15–0 (NOTE: These pins have internal pull-up

resistors.)

The following symbols appear in the Type column of Table 2:

A = asynchronous, G = ground, I = input, O = output,

P = power supply, S = synchronous, (A/D) = active drive,

(O/D) = open drain, and T = three-state.

Table 2. Pin Function Descriptions

Pin

AD15–0

RD

WR

ALE

FLAG3–0

Type

I/O/T

O

O

O

I/O/A

State During and

After Reset

Function

AD15–0 pins are

driven low both

during and after

reset

Parallel Port Address/Data. The ADSP-21261 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the

upper 16 external address bits, A23–8; ALE is used in conjunction with an external

latch to retain the values of the A23–8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the

address bits, A15–0; ALE is used in conjunction with an external latch to retain the

values of the A15–0. To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the

SYSCTL register and disable the parallel port. See Table 3 on Page 14 for a list of how

the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL

register, the IDP Channel 0 can use these pins for parallel input data.

Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or

high1

16-bit data from an external memory device. When AD15–0 are flags, this pin

remains deasserted.

Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or

high1

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted.

Output only, driven

low1

Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a

new address on the parallel port address pin. On reset, ALE is active high. However,

it can be reconfigured using software to be active low. When AD15–0 are flags, this

pin remains deasserted.

Three-state

Flag Pins. Each FLAG pin is configured via control bits as either an input or output.

As an input, it can be tested as a condition. As an output, it can be used to signal

external peripherals. These pins can be used as an SPI slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to

an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When

Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.

When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.

When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.

When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which

indicates that the system timer has expired.

Rev. 0 | Page 11 of 44 | March 2006

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