ADSP-21266 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

ADSP-21266

SHARC® Embedded Processor

Analog Devices 

ADSP-21266

for the AVDD pin. Place the filter components as close as possible

to the AVDD/AVSS pins. For an example circuit, see Figure 4. (A

recommended ferrite chip is the muRata BLM18AG102SN1D).

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for VDDINT and GND. Use wide traces

to connect the bypass capacitors to the analog power (AVDD) and

ground (AVSS) pins. Note that the AVDD and AVSS pins specified

in Figure 4 are inputs to the processor and not the analog

ground plane on the board—the AVSS pin should connect

directly to digital ground (GND) at the chip.

VDDINT

100nF

10nF

1nF

ADSP-212xx

AVDD

HI Z FERRITE

BEAD CHIP

AVSS

LOCATE ALL COMPONENTS

CLOSE TO AVDD AND AVSS PINS

Figure 4. Analog Power Filter Circuit

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor’s JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The ADSP-21266 is supported by a complete automotive refer-

ence design and development board as well as by a complete

home audio reference design board available from Analog

Devices. These boards implement complete audio decoding and

post processing algorithms that are factory programmed into

the ROM space of the ADSP-21266. SIMD optimized libraries

consume less processing resources, which results in more avail-

able processing power for custom proprietary features.

The nonvolatile memory of the ADSP-21266 can be configured

to contain a combination of Dolby Digital, Dolby Pro Logic,

Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,

and Neo:6. Multiple S/PDIF and analog I/Os are provided to

maximize end system flexibility.

The ADSP-21266 is also supported with a complete set of

CROSSCORE®† software and hardware development tools,

including Analog Devices emulators and VisualDSP++®‡

development environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21266.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The ADSP-21266

SHARC DSP has architectural features that improve the

efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tools’

command line switches

† CROSSCORE is a registered trademark of Analog Devices, Inc.

‡ VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. B | Page 9 of 44 | May 2005

Share Link: