ADSP-21367KSZ-1A データシートの表示（PDF） - Analog Devices

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ADSP-21367KSZ-1A

SHARC® Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Table 13. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Timing Requirements

tRSTVDD

RESET Low Before VDDINT/VDDEXT On

0

tIVDDEVDD

VDDINT On Before VDDEXT

–50

tCLKVDD1

CLKIN Valid After VDDINT/VDDEXT Valid

0

tCLKRST

CLKIN Valid Before RESET Deasserted

102

tPLLRST

PLL Control Setup Before RESET Deasserted

20

Max

Unit

ns

+200 ms

+200 ms

μs

μs

Switching Characteristic

tCORERST

Core Reset Deasserted After RESET Deasserted

4096tCK + 2 tCCLK 3, 4

1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume

a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

4 The 4096 cycle count depends on tsrst specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles

maximum.

RESET

VDDINT

VDDEXT

CLKIN

CLK_CFG1-0

RSTOUT

tRSTVDD

tIVDDEVDD

tCLKVDD

tCLKRST

tPLLRST

Figure 5. Power-Up Sequencing

tCO RERST

Rev. A | Page 21 of 56 | August 2006

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