ADT7476A データシートの表示（PDF） - Analog Devices
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ADT7476A Datasheet PDF : 72 Pages
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ADT7476A
ADT7476A
ADDR SELECT
VCC
10kΩ
14
PWM3/ADDREN 13 NC
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7476A TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7476A IS PLACED INTO ADDR SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
Figure 17. Unpredictable SMBus Address if Pin 13 is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7476A is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is defined as a high-to-low transition on
the serial data line SDA while the serial clock line SCL
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first), plus a R/W
bit, which determine the direction of the data transfer, that
is, whether data is written to or read from the slave device.
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, the master writes to
the slave device. If the R/W bit is a 1, the master reads from
the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and
remain stable during the high period. A low-to-high
transition, when the clock is high, can be interpreted
as a stop signal. The number of data bytes transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices
can handle.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, and then high
during the 10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the ADT7476A,
write operations contain either one or two bytes, and read
operations contain one byte.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so the correct
data register is addressed. Then, data can be written into that
register or read from it. The first byte of a write operation
always contains an address stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This write operation is illustrated in Figure 18. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
1. If the ADT7476A’s address pointer register value is
unknown, or not the desired value, then it must first be set
to the correct value before data can be read from the
desired data register. This is done by performing a write to
the ADT7476A as before, but only the data byte containing
the register address is sent, because no data is written to
the register (see Figure 19).
A read operation is then performed consisting of the serial
bus address; R/W bit set to 1, followed by the data byte
read from the data register (see Figure 20.)
2. If the address pointer register is already known to be at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 20).
Rev. 0 | Page 12 of 72
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