ADT7475 データシートの表示（PDF） - Analog Devices
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ADT7475 Datasheet PDF : 68 Pages
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ADT7475
The byte write operation is shown in Figure 18.
1
2
3
4
5 6 78
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
DATA
AP
Figure 18. Single Byte Write to a Register
READ OPERATIONS
The ADT7475 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address needs to have been set up
previously. In this operation, the master device receives a single
byte from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7475, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is shown in Figure 19.
1
2
34
S
SLAVE
ADDRESS
R
A
DATA
56
AP
Figure 19. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be con-
nected to a common SMBALERT line connected to the master.
If a device’s SMBALERT line goes low, the following events
occur:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This general call
address must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7475 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition has gone
away.
SMBus TIMEOUT
The ADT7475 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7475 assumes that the
bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some
SMBus controllers cannot handle the SMBus timeout feature,
so it can be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0; SMBus timeout enabled (default).
Bit 6 TODIS = 1; SMBus timeout disabled.
VIRUS PROTECTION
To prevent rogue programs or viruses from accessing critical
ADT7475 register settings, the lock bit can be set. Setting Bit 1
of Configuration Register 1 (0x40) sets the lock bit and locks
critical registers. In this mode, certain registers can no longer be
written to until the ADT7475 is powered down and powered up
again. For more information on which registers are locked. See
the Register Tables section.
VOLTAGE MEASUREMENT INPUT
The ADT7475 has one external voltage measurement channel.
It can also measure its own supply voltage, VCC. Pin 14 can
measure VCCP. The VCC supply voltage measurement is carried
out through the VCC pin (Pin 3). The VCCP input can be used to
monitor a chipset supply voltage in computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full scale
(decimal 768 or 300 hex) for the nominal input voltage and so
has adequate headroom to deal with overvoltages.
Rev. A | Page 12 of 68
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