ADT7475 データシートの表示（PDF） - ON Semiconductor
部品番号
コンポーネント説明
メーカー
ADT7475 Datasheet PDF : 58 Pages
| |||
ADT7475
Bit 3 (FAN2) = 1, indicates that Fan 2 has dropped below
minimum speed.
Bit 2 (FAN1) = 1, indicates that Fan 1 has dropped below
minimum speed.
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
SMBALERT Interrupt Behavior
The ADT7475 can be polled for status, or an SMBALERT
interrupt can be generated for out−of−limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
CLEARED ON READ
(TEMP BELOW LIMIT)
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 24. SMBALERT and Status Bit Behavior
Figure 24 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky because they
remain set until read by software. This ensures that an
out−of−limit event cannot be missed if software is polling
the device periodically. Note that the SMBALERT output
remains low for the entire duration that a reading is
out−of−limit and until the interrupt status register has been
read. This has implications for how software handles the
interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommended to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(0x74 and 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 25.
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT CLEARED
(SMBALERT RE−ARMED)
Figure 25. How Masking the Interrupt Source Affects
SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Register 1 (0x74) and Interrupt Mask
Register 2 (0x75) allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2
Temperature.
Bit 5 (LT) = 1, masks SMBALERT for Local Temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1
Temperature.
Bit 2 (VCC) = 1, masks SMBALERT for VCC Channel.
Bit 0 (VCCP) = 1, masks SMBALERT for VCCP Channel.
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (F4P) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by
default. Pin 5 or Pin 9 can be reconfigured as an
SMBALERT output to signal out−of−limit conditions.
http://onsemi.com
18
Share Link: 