ADV7152L データシートの表示（PDF） - Analog Devices

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ADV7152L

CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC

Analog Devices 

ADV7152

Alternatively, the ADV7152 CLOCK inputs can be driven by a If it is not necessary to have a known fixed number of pipeline

Programmable Clock Generator (Figure 13), such as the

delays, then there is no limitation on the delay between LOAD-

ICS1562. The ICS1562 is a monolithic, phase-locked-loop,

OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).

clock generator chip. It is capable of synthesizing differential

LOADIN and Pixel Data must conform to the setup and hold

ECL output frequencies in a range up to 220 MHz from a single times (t8 and t9).

low frequency reference crystal.

If however, it is required that the ADV7152 has a fixed number

LOW FREQUENCY

of pipeline delays (tPD), LOADOUT and LOADIN must con-

OSCILLATOR

GND

VCC

VCC

VAA

form to timing specifications t10 and τ-t11 as illustrated in Fig-

ures 4 and 5.

+5V

PRGCKOUT

VCLOCK

220Ω

220Ω

The PRGCKOUT control signal outputs a user programmable

ECLOUT+

CLOCK

clock frequency. It is a divided down frequency of the pixel

OBSOLETE +5V ECLOUT–

CLOCK

GENERATOR

VREF OUT

330Ω

330Ω

GND

GND

VAA

0.1 µF

CLOCK

ADV7152

VREF

GND

D0–D3 CS R/W

GND

Figure 13. PLL Generator Driving CLOCK, CLOCK of the

ADV7152

CLOCK CONTROL SIGNALS LOADOUT

The ADV7152 generates a LOADOUT control signal which

runs at a divided down frequency of the pixel CLOCK. The

CLOCK (see Figure 8). The rising edge of PRGCKOUT is

synchronous to the rising edge of LOADOUT

fPRGCKOUT = f CLOCK/N

where N = 4, 8, 16 or 32.

One application of the PRGCKOUT is to use it as the master

clock frequency of the graphics subsystems processor or

controller.

SCKIN, SCKOUT

These video memory signals are used to minimize external sup-

port chips. Figure 15 illustrates the function that is provided.

An input signal applied to SCKIN is synchronously AND-ed

with the video blanking signal (BLANK). The resulting signal is

output on SCKOUT. Figure 7 of the Timing Waveform section

shows the relationship between SCKOUT, SCKIN and

BLANK.

frequency is automatically set to the programmed multiplex

rate, controlled by CR36 of Command Register 3.

SCKOUT

LATCH

fLOADOUT = fCLOCK/2

fLOADOUT = fCLOCK

2:1 Multiplex Mode

1:1 Multiplex Mode

The LOADOUT signal is used to directly drive the LOADIN

BLANK

SYNC

SCKIN

ENABLE

pixel latch signal of the ADV7152. This is most simply achieved

by tying the LOADOUT and LOADIN pins together. Alterna-

tively, the LOADOUT signal can be used to drive the frame

buffer’s shift clock signals, returning to the LOADIN input de-

layed with respect to LOADOUT.

Figure 15. SCKOUT Generation Circuit

The SCKOUT signal is essentially the video memory shift con-

trol signal. It is stopped during the screen retrace. Figure 16

shows a suggested frame buffer to ADV7152 interface. This is a

LOADOUT

LOADOUT(1)

LOADOUT

minimum chip solution and allows the ADV7152 control the

overall graphics system clocking and synchronization.

VIDEO

FRAME

BUFFER

ADV7152

LOADIN

VIDEO

FRAME

BUFFER LOADOUT(2)

ADV7152

LOADIN

LOADOUT

PIXEL

DATA

PIXEL

DATA

VIDEO

FRAME

BUFFER

LOADIN

SCKIN

ADV7152

BLANK

LOADOUT

LOADOUT(1)

SCKOUT

LOADIN

LOADOUT(2)

DELAY

PIXEL

DATA

Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)

Figure 16. ADV7152 Interface Using SCKIN and SCKOUT

–12–

REV. B

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