AIT1042RS38P9 データシートの表示（PDF） - ANADIGICS

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AIT1042RS38P9

Integrated Digital Tuner with RF and IF Gain Control

ANADIGICS 

AIT1042

Synthesizer Programming Example

The following is an example for programming the two synthesizers in the AIT1042 device. The calculations

will determine the values required to input into the four main registers:

• Main divider and reference divider for the upconverter

• Main divider and reference divider for the downconverter.

Conditions

The desired CATV frequency to receive is 55.25MHz (picture carrier).

The 1st IF (HIF) is 1690.75MHz and the 2nd IF is 45.75MHz.

Phase detector comparison frequency for the upconverter is 2000KHz (2MHz).

Phase detector comparison frequency for the downconverter is 62.5KHz.

The crystal (xtal) reference oscillator frequency is 16MHz

The preset modulus of the prescalar for: Upconverter - P = 16 and for Downconveter – P = 64.

Calculation of the Reference Divider Values

The value for each reference divider can be calculated by dividing the reference oscillator frequency by the

desired phase detector comparison frequency:

R = Fref.osc./FPD

For the upconverter, the 16MHz crystal oscillator frequency and the 2000KHz phase detector comparison

frequency are used to get:

RPLL1 = 16MHz/2000KHz(2MHz) = 8. Therefore, the bit values for the upconverter reference divider regis-

ter would be: 0000001000

For the downconverter, the 16MHz crystal oscillator frequency and the 62.5KHz phase detector comparison

frequency are used to get: RPLL2 = 16MHz/62.5KHz (0.625MHz) = 256. Therefore, the bit values for the

downconverter reference divider register would be:

0100000000

Main Divider Register Calculations

The values of the A and B counters are determined by the desired VCO output frequency of the on-chip local

oscillators and the phase detector comparison frequency:

N = FVCO/FPD B = trunc(N/P) A = N – (B x P)

The upconverter local oscillator frequency will be 1690.75MHz + 55.25MHz = 1746MHz for this example.

Therefore, the N value for PLL1 will be = 1746MHz/2MHz = 873, the B value for PLL1 will be = (873/16) =

54, and the A value for PLL1 will be = 873 – (54 x 16) = 9. The upconverter main divider register value will

be: B = 00000110110, A = 0001001

The downconverter local oscillator frequency will be 1690.75 – 45.75MHz = 1645MHz.

Therefore, the N values for PLL2 will be 1645MHz/62.5KHz = 26320, the B value for PLL2 will be =

(26320/64) = 411, and the A value for PLL2 will be = 26320 – (411 x 64) = 16. The downconverter main

register value will be: B = 00110011011, A = 0010000

16

PRELIMINARY DATA SHEET - Rev 1.0

02/2009

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