CY7C4201-15ACT データシートの表示（PDF） - Cypress Semiconductor
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CY7C4201-15ACT Datasheet PDF : 18 Pages
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Switching Waveforms (continued)
Programmable Almost Full Flag Timing
tCLKH
tCLKL
WCLK
WEN1
tENS tENH
WEN2
(if applicable)
PAF
tENS tENH
FULL − M+1 WORDS
IN FIFO
RCLK
REN1,
REN2
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Note
25
Note
26
tPAF
FULL − M WORDS
IN FIFO [27]
tSKEW2[28]
tENS
tENS tENH
tPAF
Write Programmable Registers
tCLKH
tCLK
tCLKL
WCLK
WEN2/LD
tENS
tENH
WEN1
tENS
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
22. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
23. PAE offset = n.
24. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
25. If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW.
26. PAF offset = m.
27. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,
4096 – m words for CY7C4241, 8192 – m words for CY7C4251.
28. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *B
Page 12 of 18
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