UPD43256BGU-70L-A データシートの表示（PDF） - NEC => Renesas Technology

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UPD43256BGU-70L-A

256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT 85ns

NEC => Renesas Technology 

μPD43256B

Write Cycle Timing Chart 2 (/CS Controlled)

Address (Input)

/CS (Input)

/WE (Input)

tWC

tAS

tCW

tAW

tWP

tWR

I/O (Input)

High impedance

tDW

Data in

tDH

High

impedance

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. When I/O pins are in the output state, therefore the input signals must not be applied to

the output.

Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.

16

Data Sheet M10770EJEV0DS

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