HM5225325F データシートの表示（PDF） - Hitachi -> Renesas Electronics

部品番号

コンポーネント説明

メーカー

HM5225325F

256M LVTTL interface SDRAM 100 MHz 1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank PC/100 SDRAM

Hitachi -> Renesas Electronics 

HM5225645F-B60, HM5225325F-B60

Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.

2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.

3. tLZ (min) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max) defines the time at which the outputs achieves the high impedance state.

5. tCES define CKE setup time to CLK rising edge except power down exit command.

6. tAS/tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM.

tDS/tDH: Data-in, tCES/tCEH: CKE

Test Conditions

• Input and output timing reference levels: 1.5 V

• Input waveform and output load: See following figures

input

2.4 V

2.0 V

0.4 V 0.8 V

tT

tT

I/O

CL

13

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