AM29LV200BB-55RSE データシートの表示（PDF） - Advanced Micro Devices

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AM29LV200BB-55RSE

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

DATA SHEET

START

RESET# = VID

(Note 1)

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadver tent writes (refer to Table 5 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not

accept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

14

Am29LV200B

21521D6 October 10, 2006

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