AM79C901AJC データシートの表示（PDF） - Advanced Micro Devices

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AM79C901AJC

HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY

Advanced Micro Devices 

PRELIMINARY

PIN DESCRIPTIONS

Configuration Pins

MII/GPSI

MII/GPSI

Input

MII/GPSI selects between the MII and the GPSI inter-

face. This pin must be connected to either VDD or VSS.

Changing the state of this pin is prohibited.

GM_MODE

GM_MODE

Input

This input pin selects between the MDC/MDIO com-

mand and control interface and the SPI interface nor-

mally available in the GPSI mode. This pin must be

connected to either VDD or VSS. Changing the state of

this pin is prohibited.

Data

Command and

GM_MODE MII/GPSI Interface Control Interface

0

1

MII

MDC/MDIO

0

0

GPSI

SPI

1

X

GPSI

MDC/MDIO

Note: GM_MODE = 1 overrides the value on the

MII/GPSI configuration pin.

PHY_AD

PHY Address

Input

Sets bit 2 of the PHY Address field. The PHYs have de-

fault MII address of 0x00 (0000b) for the 1 Mbps

HomePNA PHY and 0x01 (0001b) for the 10BASE-T

PHY. If this bit is set, the address for the HomePNA

PHY is 0x02 (00010b) and 0x03 (00011b) for the

10BASE-T PHY.

ISOLATE

Isolate

Input

In an environment that utilizes the MII or the SPI com-

mand and control interface (managed mode), this pin

must be held HIGH. In an environment that does not

use the MII or the SPI command and control interface

(external control mode), this pin enables the data inter-

face when set to a LOW, and forces the interface into a

high impedance state when held HIGH. This pin func-

tions in conjunction with the PHY_SEL pin and HPR0,

bit 10, and TBR0, bit 10.

PHY_SEL

PHY Select

Input

In an environment that utilizes the MII or the SPI com-

mand and control interface (managed mode), this pin

must be held LOW. In an environment that does not use

the MII or the SPI command and control interface (ex-

ternal control mode), this pin selects which PHY data

and status signals will be driven onto the interface.

When set to a LOW, the HomePNA PHY data and sta-

tus signals will be driven onto the interface. When set

to a HIGH, the 10BASE-T PHY data and status signals

will be driven onto the interface. This pin functions in

conjunction with the ISOLATE pin.

LOW = 1 Mbps HomePNA PHY

HIGH = 10BASE-T PHY

HPR0 TBR0

Bit 10 Bit 10 PHY_SEL ISOLATE

Managed Mode

1

1

0

1

0

1

0

1

1

0

0

1

0

0

0

1

External Control Mode

1

1

1

0

1

1

0

0

1

1

Don’t

Care

1

Interface

Source

Hi Z

1 Mbps

HomePNA

10BASE-T

Non Valid

10BASE-T

1 Mbps

HomePNA

Hi Z

Board Interface

LED_COL

LED_COL

Output

This output is designed to directly drive an LED. COL

low indicates that a collision has been detected on

the currently active PHY. An internal pulse stretching

circuit will ensure that the minimum output pulse is

approximately 100 ms.

LED_ACTIVITY

LED_ACTIVITY

Output

This output is designed to directly drive an LED.

ACTIVITY low indicates that there is receive or trans-

mit activity on the network of the currently active PHY.

An internal pulse stretching circuit will ensure that the

minimum output pulse is approximately 100 ms.

LED_LINK

LED_LINK

Output

This output is designed to directly drive an LED. LINK

low indicates that a valid link has been detected on the

currently active PHY.

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Am79C901A

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