AMD-X5-133 データシートの表示（PDF） - Advanced Micro Devices

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AMD-X5-133

Am5X86™ Microprocessor Family

Advanced Micro Devices 

PRELIMINARY

AMD

4.8.3 External Bus Master Snooping Actions

The following scenarios describe the snooping actions

of an external bus master.

sertion. In the fastest case, this means that

HOLD was asserted one clock cycle before the

HLDA response.

4.8.3.1 Snoop Miss

Scenario: A snoop of the on-chip cache does not hit a

line, as shown in Figure 6.

Step 2 EADS and INV are applied to the microproces-

sor. If INV is 0, a read access caused the snoop-

ing cycle. If INV is 1, a write access caused the

snooping cycle.

Step 1 The microprocessor is placed in Snooping

mode with HOLD. HLDA must be High for a

minimum of one clock cycle before EADS as-

sertion. In the fastest case, this means that

HOLD was asserted one clock cycle before the

HLDA response.

Step 2 EADS and INV are applied to the microproces-

sor. If INV is 0, a read access caused the snoop-

ing cycle. If INV is 1, a write access caused the

snooping cycle.

Step 3 Two clock cycles after EADS is asserted, HITM

becomes valid. Because the addressed line is

not in the snooping cache, HITM is 1.

4.8.3.2 Snoop Hit to a Non-Modified Line

Scenario: The snoop of the on-chip cache hits a line,

and the line is not modified (see Figure 7).

Step 1 The microprocessor is placed in Snooping

mode with HOLD. HLDA must be High for a

minimum of one clock cycle before EADS as-

Step 3 Two clock cycles after EADS is asserted, HITM

becomes valid. In this case, HITM is 1.

4.8.4 Write-Back Case

Scenario: Write-back accesses are always burst writes

with a length of four 32-bit words. For burst writes, the

burst always starts with the microprocessor line offset

at 0. HOLD must be deasserted before the write-back

can be performed (see Figure 8).

Step 1 HOLD places the microprocessor in Snooping

mode. HLDA must be High for a minimum of

one clock cycle before EADS assertion. In the

fastest case, this means that HOLD asserts one

clock cycle before the HLDA response.

Step 2 EADS and INV are asserted. If INV is 0, snoop-

ing is caused by a read access. If INV is 1,

snooping is caused by a write access. EADS is

not sampled again until after the modified line

is written back to memory. It is detected again

as early as in Step 11.

CLK

ADR

M/IO

CACHE

W/R

ADS

n

floating/tri-stated

n

n+4 n+8 n+1

5

n

floating/tri-stated

BLAST

BRDY

11

6

INV

EADS

valid

2

3

valid

HITM

HOLD

1

4

HLDA

78

9

Data

External

bus master’s

BOFF signal

n n+4 n+8 n+12

Note:

The circled numbers in this figure represent the steps in section 4.8.4.

Figure 8. Snoop That Hits a Modified Line (Write-Back)

Am5X86 Microprocessor

10

25

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