APL1117-UC-TR データシートの表示（PDF） - Anpec Electronics
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APL1117-UC-TR
Anpec Electronics
APL1117-UC-TR Datasheet PDF : 18 Pages
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APL1117
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimension
t
E
Po
P
D
P1
F
Bo
W
Ao
D1
Ko
T2
J
C
A
B
T1
A p p lic a tion
TO -252
A
330 ±3
F
B
100 ± 2
D
C
13 ± 0. 5
D1
J
2 ± 0 .5
Po
T1
1 6.4 + 0 .3
-0 .2
P1
T2
2 .5 ± 0 .5
Ao
W
1 6+ 0.3
- 0 .1
Bo
P
8 ± 0 .1
Ko
E
1.75 ± 0.1
t
7 .5 ± 0 .1
A p p lic a tion
A
380±3
TO -263
F
11 .5 ± 0 .1
A p p lic a tion
A
330±1
S O T-223
F
1 .5 + 0.1
B
80 ± 2
D
1 .5 + 0.1
B
6 2 ±1 .5
D
1 .5± 0 .25
C
13 ± 0. 5
D1
4 .0 ± 0 .1
J
2 ± 0 .5
Po
2 .0 ± 0 .1
T1
24 ± 4
P1
6 .8 ± 0 .1 1 0 .4 ± 0 .1
T2
2± 0 .3
W
2 4 + 0.3
- 0 .1
Ao
Bo
1 .5± 0 .25
C
1 2 .7 5 ±
0 .1 5
D1
4 .0 ± 0 .1
J
2 ± 0 .6
Po
2 .0 ± 0 .1 1 0 .8 ± 0 .1 1 6 .1 ± 0 .1
T1
T2
W
1 2.4 + 0.2 2± 0 .2 1 2 ± 0 .3
P1
Ao
Bo
2 .5± 0 .1 0 .3 ±0 .05
P
E
1 6 ± 0 .1 1 .7 5 ± 0 .1
Ko
5 .2± 0 .1
P
t
0 .3 5 ± 0 .0 1
3
E
8 ± 0 .1 1 .7 5 ± 0 .1
Ko
t
5 .5 ± 0 .0 5 1 .5 + 0 .1 1 .5 + 0 .1 4 .0 ± 0 .1 2 .0 ± 0 .0 5 6 .9 ± 0 .1 7 .5 ± 0 .1 2 .1 ± 0 .1 0 .3 ± 0 .0 5
Copyright ANPEC Electronics Corp.
17
Rev. B.8 - Jun., 2003
www.anpec.com.tw
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