24LLC02
2K-bit Serial EEPROM for Low Power
SDA
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
WP
EEPROM
Cell Array
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
256 x 8 bits
A0
A1
A2
Column Decoder
DOUT and ACK
Data Register
Figure 1-1. 24LLC02 Block Diagram
* All specs and applications shown above subject to change without prior notice.
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Rev 1.2 May 6,2002