APW7057KC-TRG データシートの表示（PDF） - Anpec Electronics

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APW7057KC-TRG

High Power Step-Down Synchronous DC/DC Controller

Anpec Electronics 

APW7057

Application Information

Layout Consideration (Cont.)

Below is a checklist for your layout:

• Keep the switching nodes (UGATE, LGATE, and

PHASE) away from sensitive small signal nodes since

these nodes are fast moving signals. Therefore, keep

traces to these nodes as short as possible.

•

Decoupling

capacitor

C

IN

provides

the

bulk

capacitance

and needs to be placed close to the IC since it will

provide the MOSFET drivers transient current

requirement.

• The ground return of CIN must return to the combine

COUT (-) terminal.

• Capacitor CBOOT should be connected as close to the

BOOT and PHASE pins as possible.

• Capacitor CHF is to improve noise performance and a

small 1µF ceramic capacitor will be sufficient.

CHF

VIN

VCC 5

BOOT 1

CIN

+

LGATE 4

APW7057

U

1 UGATE

2

PHASE 8

Q1

Q2

COUT

+

L1

VOUT

Figure 4. Recommended Layout Diagram

V DS

t sw

Time

Figure 3. Switching waveform across MOSFET

Copyright © ANPEC Electronics Corp.

11

Rev. A.5 - Jun., 2008

www.anpec.com.tw

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