APW7334 データシートの表示（PDF） - Anpec Electronics
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APW7334 Datasheet PDF : 15 Pages
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APW7334
Application Information (Cont.)
Thermal Consideration
The APW7334 maximum power dissipation depends on
the thermal resistance and temperature difference be-
tween the die junction and ambient air. The power dissi-
pation PD across the device is:
P
D
=
(T
J
-
T)
A
/
θJA
where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
between Junction and ambient air.
For normal operation, do not exceed the maximum junc-
tion temperature rating of TJ = 125oC. The calculated
power dissipation should less than:
PD = (125-25)/110=0.90(W)-----(SOP-8)
2.5
2
1.5
1
0.5
0
0
SOP-8
25
50
75
100
125
Ambient Temperature, TA(oC)
1. Begin the layout by placing the power components first.
Orient the power circuitry to achieve a clean power flow
path. If possible, make all the connections on one side of
the PCB with wide, copper filled areas.
2. In Figure 3, the loops with same color bold lines con-
duct high slew rate current. These interconnecting im-
pedances should be minimized by using wide and short
printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB
and it should be placed near the IC as close as possible.
Therefore, place the feedback divider and the feedback
compensation network close to the IC to avoid switching
noise. Connect the ground of feedback divider directly to
the GND pin of the IC using a dedicated ground trace.
4. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground plane
to connect the C1, C2, and Schottky diode to provide a low
impedance path between the components for large and
high slew rate current.
+
VIN
-
VIN BS
Compensation
Network
EN U1 LX
APW7334
COMP
R3
FB
C5
GND
C1
L1
C3
R1
R2
+
C2 Load VOUT
-
Feedback
Divider
Layout Consideration
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separating and finally
combined using the ground plane construction or single
point grounding. Figure 3 illustrates the layout, with bold
lines indicating high current paths. Components along
the bold lines should be placed close together. Below is
a checklist for your layout:
Figure 2. Current Path Diagram
Sensitive node (FB, COMP) should be away from
switching node(LX) and it should be placed near
the IC with short trace
Numerous vias connected from
the thermal pad to the
solderside ground plane(s)
should be used to enhance heat
dissipation
APW7334
SOP-8
Ground
Input Capacitor C1 should be
near the IC as close as possible
VIN
L1
VLX
VOUT
C2
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
Power path should be short and wide
Figure 3. Recommended Layout Diagram
10
www.anpec.com.tw
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