AS1331(Rev1-03) データシートの表示（PDF） - austriamicrosystems AG
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AS1331 Datasheet PDF : 16 Pages
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AS1331
Datasheet - Detailed Description
8 Detailed Description
The synchronous buck-boost converter AS1331 uses a Power Save Mode control technique to reach a high efficiency
over a wide dynamic range of load currents. The output voltage is monitored by a comparator with 3% accuracy. The
Power Save Mode puts the device into “sleep mode” when VOUT is above its programmed reference threshold.
Meaning, the switching is stopped and only quiescent current is drawn from the power source. The switching is started
again when VOUT drops below the reference threshold and the output capacitor is charged again.
The numbers of current pulses which are necessary to load the output capacitor are set by the value of the output
capacitor, the load current, and the comparator hysteresis (~1%).
Figure 23. AS1331 - Block Diagram - Fixed Output Voltage
SW1
SW2
SW A
VIN
SW D
VOUT
SW B
AS1331
Gate Drivers
and
Anticross
Conduction
SW C
IZERO
Detect
Peak
Current
600mA Limit
VIN
1.6V
UVLO
State
Machine
and
Logic
EN
Shutdown
Thermal Shutdown
VBEST
VBEST
VIN
VOUT
VOUT
Comp
1.25V
R1
PGND
GND
FB
R2
Modes of Operation
When VOUT drops below the reference threshold, the AS1331 switches on the transistors SW A and SW C until the
inductor current reaches approximately 400mA. In the next step SW A and SW D are closed and depending on the
difference between VIN and VOUT the inductor current raises, falls or stays constant.
VIN > VOUT: The inductor current is going up to 600mA.
VIN ~ VOUT: The device stops after 2µs.
VIN < VOUT: The inductor current falls down to 0mA.
If the inductor current is not 0mA, the transistors SW B and SW D are closed to ramp down the current to zero. If VOUT
is still below the threshold voltage the next cycle is started. If IMAX (600mA) wasn’t reached in the previous cycle, SW A
and SW D are closed until the inductor current is 600mA.
Note: The 4-switch-mode (SW A+SW C => SW B+SW D => SW A + SW C...) and also the buck-mode (SW A+SW D
=> SW B+SW D => SW A+SW D...) are never used.
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Revision 1.03
10 - 16
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