AS3909 データシートの表示（PDF） - austriamicrosystems AG
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AS3909 Datasheet PDF : 77 Pages
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AS3909/AS3910 – 12
Detailed Description
A/D conversion of signal applied to pin AD_IN). The result of
A/D conversion is stored in a register, which can be read through
the SPI interface.
External Field Detector
The external field detector is a low power block, which is
switched on in NFCIP target mode to detect the presence of
initiator field. It is also used during the NFCIP Collision
Avoidance procedure.
Quartz Crystal Oscillator
The quartz crystal oscillator can operate with 13.56MHz and
27.12MHz crystals. At start-up the transconductance of the
oscillator is increased to achieve fast start-up. Since the start-up
time varies depending on crystal type, temperature and other
parameters, the oscillator amplitude is observed and an
interrupt is sent when stable operation is reached to inform the
controller that the clock signal is stable and reader field can be
switched on.
It also provides a clock signal to the external microcontroller
(MCU_CLK) according to setting in the control register.
Power Supply Regulators
Integrated power supply regulators ensure high power supply
rejection of a complete reader system. At power up, the
regulators are transparent. In case PSRR of the reader system
has to be improved, then the command Adjust Regulators is
sent. As a result of this command, the power supply level of VDD
is measured in maximum load conditions and the regulated
voltage reference is set 250mV below this measured level to
assure a stable regulated supply. The resulting regulated
voltage is stored in a register. It is also possible to define
regulated voltage by writing a configuration register. In order
to decouple any noise sources from different parts of IC there
are two regulators integrated with separated external blocking
capacitors (regulated voltage of both is the same). One
regulator is for the analog blocks, the other one is for the
antenna drivers. Logic and digital I/O pads are supplied directly
from VDD (negative supply pin for logic and digital I/O is
separated to avoid coupling of logic induced noise in the
substrate). This block additionally generates a reference
voltage for the analog processing (AGD - analog ground).
This voltage also has an associated external buffer capacitor.
POR and Bias
This block contains the bias current and voltage generator,
which provides bias currents and reference voltages to all other
blocks. It also incorporates a Power on Reset (POR) circuit, which
provides a reset at power-up and at low supply levels.
ams Datasheet, Confidential: 2013-Oct [3-02]
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