NX26F640C データシートの表示（PDF） - NexFlash -> Winbond Electronics

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NX26F640C

64M-BIT SERIAL FLASH MEMORY WITH 2-PIN NXS2 INTERFACE

NexFlash -> Winbond Electronics 

NX26F640C

Refresh Sector commands are used. Reading from the

SRAM is accomplished by first bringing CS low then shift-

ing in the Read SRAM command (71H or 73H) followed

by its 16-bit “byte-address” field is clocked into the device

to designate the starting location within the 522-byte sec-

tor. Only B[9:0] of the byte-address field are used; the

uppermost bits are not used but must be clocked in (use 0

for data). Only byte-addresses of 0 to 209H (522 bytes)

are valid. Following the byte-address field, 8 control clocks

are required with data=0. The Serial Data

Output (SO) will change from a high-impedance state and

begin to drive the output. If SO uses the rising edge of

clock (configuration register RCE=1), the output will be

driven after the last control clock. If SO uses the falling

edge of clock (RCE=0), the output will be driven on the

next falling edge of clock. The data field is shifted out with

the least significant byte first (i.e., byte-00H, byte-01H,

...). The bit order within each byte is the most significant

bit first (i.e.,D7,...D0). The byte-address is internally

incremented to the next higher byte address as the clock

continues.

SERIAL FLASH SECTOR AND SRAM

WRITE COMMANDS

Write Enable (06H)

Upon power-up, the Flash memory array is write- protected

until the Write Enable command (06H) has been issued.

The WP pin must be inactive while writing the command

for the write enable to be accepted. The status of the

device’s write protect state can be read in the status reg-

ister. The Write Enable command sequence is completed

by asserting CS high after eight additional clocks.

Write Disable (04H)

The Write Disable command (04H) protects the Flash

memory array from being programmed. Once issued,

further Write to Sector or Transfer SRAM to Sector com-

mands will be ignored. The status of the write protect state

can be read in the status register. The Write Disable com-

mand sequence is completed by asserting CS high after

eight additional clocks.

Write to Sector Using SRAM (F6H or 98H)

Before writing to a sector in the Flash memory array, all

hardware and software write protection must be in an

enabled state. This means that the WP pin must be in a

high state, a Write Enable command must have previ-

ously been issued, and the sector location that is to be

written to must be outside the write protect range set in

the configuration register. Additionally, the Ready/Busy

status should be checked to confirm that the memory

array is available to be written to, refer to figures 8 and

12 for block diagram.

Writing to a sector is accomplished by first bringing CS

low and shifting in the Write to Sector Using SRAM com-

mand (F6H or 98H) followed by a 16-bit “sector-address”

field. Although the sector-address field is 16-bits, only

bits S[13:0] are used. The uppermost sector address

bits are not used but must be clocked in (use 0 data).

Following the sector address, a 16-bit “byte-address”

field is clocked into the device to designate the starting

location within the 522-byte sector. Only bits B[9:0] of

the byte-address field are used and only values of

0-209H (522 bytes) are valid.

After the byte-address has been loaded, data is shifted

into the 522-byte SRAM, which serves as a temporary

storage buffer. Existing data in the SRAM will be

written over. The byte order of the data shifted into the

SRAM is least significant byte first (i.e., byte-00H,

byte-01H,...). The bit order within each byte is most sig-

nificant bit first (i.e., D7,...D0). The byte-address is

automatically incremented to the next higher byte ad-

dress as the clock continues. When the last byte ad-

dress to be written is reached, the command can be

completed with an additional eight control clocks (with

data=0) followed by asserting CS high.

After the CS pin is brought high, the data in the SRAM is

transferred to the specified sector in memory array. See

tWP timing specifications. During this time the array and

SRAM will be “busy” and will ignore further array-related

commands until complete. All Ready/Busy status indica-

tors will indicate a busy status.

16

NexFlash Technologies, Inc.

PRELIMINARY NXSF020D-0902

09/05/02 ©

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