AT25P1024C1-10CI-2.7_06 データシートの表示（PDF） - Atmel Corporation

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AT25P1024C1-10CI-2.7_06

SPI Serial EEPROMs

Atmel Corporation 

Functional

Description

AT25P1024

The AT25P1024 is designed to interface directly with the synchronous serial peripheral

interface (SPI) of the 6800 type series of microcontrollers.

The AT25P1024 utilizes an 8-bit instruction register. The list of instructions and their

operation codes are contained in Table 5. All instructions, addresses, and data are

transferred with the MSB first and start with a high-to-low transition.

Table 5. Instruction Set for the AT25P1024

Instruction Name

Instruction Format

Operation

WREN

0000 X110

Set Write Enable Latch

WRDI

0000 X100

Reset Write Enable Latch

RDSR

0000 X101

Read Status Register

WRSR

0000 X001

Write Status Register

READ

0000 X011

Read Data from Memory Array

WRITE

0000 X010

Write Data to Memory Array

WRITE ENABLE (WREN): The device will power up in the write disable state when VCC

is applied. All programming instructions must therefore be preceded by a Write Enable

instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write

Disable instruction disables all programming modes. The WRDI instruction is indepen-

dent of the status of the WP pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides

access to the status register. The Ready/Busy and Write Enable status of the device

can be determined by the RDSR instruction. Similarly, the block write protection bits

indicate the extent of protection employed. These bits are set by using the WRSR

instruction.

Table 6. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

WPEN

X

X

X

Bit 3

BP1

Bit 2

BP0

Bit 1

WEN

Bit 0

RDY

7

1082I–SEEPR–7/06

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