AT52BC6402AT-85CI データシートの表示（PDF） - Atmel Corporation

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AT52BC6402AT-85CI

64-Mbit Flash, 16-Mbit PSRAM (x16 I/O)

Atmel Corporation 

AC Asynchronous Read Timing Characteristics

Symbol

tACC

tCE

tOE

tDF

tRO

Parameter

Access, Address to Data Valid

Access, CE to Data Valid

OE to Data Valid

CE, OE High to Data Float

RESET to Output Delay

64-Mbit-70

Min

Max

70

70

20

25

150

Asynchronous Read Cycle Waveform(1)(2)(3)

A0 - A21

tRC

ADDRESS VALID

CE

64-Mbit-85

Min

Max

85

85

20

25

150

Units

ns

ns

ns

ns

ns

tCE

OE

tOE

tACC

tDF

tOH

RESET

tRO

I/O0 - I/O15

HIGH Z

OUTPUT

VALID

Notes:

1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

20 AT52BC6402A(T)

3441B–STKD–11/04

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