AT52BC6402AT データシートの表示（PDF） - Atmel Corporation
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AT52BC6402AT Datasheet PDF : 38 Pages
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Read Cycle 1(1),(4)
ADDRESS
CS1
CS2
VIH
UB, LB
PSOE
DATA OUT
HIGH-Z
tRC
tAA
tACS
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
DATA VALID
Read Cycle 2, CS2 = VIH(1),(2),(4)
tRC
ADDRESS
tAA
tOH
DATA OUT
PREVIOUS DATA
tOH
DATA VALID
Read Cycle 3, CS2 = VIH(1),(2),(4)
CS1
DATA OUT
HIGH-Z
tACS
t (3)
CLZ
t (3)
CHZ
DATA VALID
Notes:
1. Read Cycle occurs whenever a high on the PSWE and PSOE is low, while UB and/or LB and CS1 and CS2 are in
active status.
2. PSOE = VIL.
3. The tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ, tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output
voltage levels.
4. CS1 in high for the standby, low for active.
32 AT52BC6402A(T)
3441B–STKD–11/04
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